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PRELIMINARY DATA SHEET
512MB Registered DDR SDRAM DIMM
EBD51RD8ABFA (64M words x 72 bits, 1 Rank)
Description
The EBD51RD8ABFA is a 64M words x 72 bits, 1 rank Double Data Rate (DDR) SDRAM Module, mounting 9 pieces of DDR SDRAM sealed in TSOP package. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2-bit prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each TSOP on the module board.
Features
* 184-pin socket type dual in line memory module (DIMM) PCB height: 30.48mm Lead pitch: 1.27mm * 2.5V power supply * Data rate: 333Mbps/266Mbps (max.) * 2.5 V (SSTL_2 compatible) I/O * Double Data Rate architecture; two data transfers per clock cycle * Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver * Data inputs and outputs are synchronized with DQS * 4 internal banks for concurrent operation (Component) * DQS is edge aligned with data for READs; center aligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive CK edge; data referenced to both edges of DQS * Data mask (DM) for write data * Auto precharge option for each burst access * Programmable burst length: 2, 4, 8 * Programmable /CAS latency (CL): 2, 2.5 * Refresh cycles: (8192 refresh cycles /64ms) 7.8s maximum average periodic refresh interval * 2 variations of refresh Auto refresh Self refresh * 1 piece of PLL clock driver, 2 pieces of register drivers and 1 piece of serial EEPROM (2k bits EEPROM) for Presence Detect (PD)
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Document No. E0376E10 (Ver. 1.0) Date Published April 2003 (K) Japan URL: http://www.elpida.com
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This product became EOL in March, 2004.
Elpida Memory,Inc. 2003
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EBD51RD8ABFA
Ordering Information
Data rate Mbps (max.) 333 266 Component JEDEC speed bin*1 (CL-tRCD-tRP) DDR333B (2.5-3-3) DDR266A (2-3-3) DDR266B (2.5-3-3) Contact pad Gold
Part number EBD51RD8ABFA-6B EBD51RD8ABFA-7A EBD51RD8ABFA-7B
Package 184-pin DIMM
Mounted devices EDD5108ABTA-6B EDD5108ABTA-6B, -7A EDD5108ABTA-6B, -7A, -7B
Notes: 1. Module /CAS latency = component CL + 1.
Pin Configurations
Front side 1 pin 52 pin 53 pin 92 pin
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Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Pin name VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC /RESET VSS DQ8 DQ9 DQS1 VDD NC NC VSS DQ10 DQ11 CKE0 VDD DQ16 DQ17 DQS2 VSS A9
93 pin Back side
144 pin 145 pin 184 pin
Pin No. 47 48
Pin name DQS8 A0 CB2 VSS CB3 BA1
Pin No. 93 94 95 96 97 98
Pin name VSS DQ4 DQ5 VDD DM0/DQS9 DQ6 DQ7 VSS NC NC NC VDD
Pin No. 139 140 141 142 143 144 145 146 147 148 149 150
Pin name VSS DM8/DQS17 A10 CB6 VDD CB7 VSS DQ36 DQ37 VDD DM4/DQS13 DQ38 DQ39 VSS DQ44 /RAS DQ45 VDD /CS0
Preliminary Data Sheet E0376E10 (Ver. 1.0)
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49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73
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DQ32 99 VDD 100 DQ33 101 DQS4 102 DQ34 VSS BA0 DQ35 DQ40 VDD /WE DQ41 /CAS VSS DQS5 DQ42 DQ43 VDD NC DQ48 DQ49 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119
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DQ12 151 DQ13 152 DM1/DQS10 153 154 VDD DQ14 155 DQ15 NC VDD NC 156 157 158 159 DQ20 A12 VSS 160 161 162 DQ21 A11 163 164 DM2/DQS11 165
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NC DM5/DQS14 VSS DQ46 DQ47 NC VDD DQ52
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EBD51RD8ABFA
Pin No. 28 29 30 31 32 33 34 35 36 37 38 39 Pin name DQ18 A7 VDD DQ19 A5 DQ24 VSS DQ25 DQS3 A4 VDD Pin No. 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Pin name VSS NC NC VDD DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL Pin No. 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 Pin name VDD DQ22 A8 DQ23 VSS A6 DQ28 DQ29 VDD DM3/DQS12 A3 DQ30 VSS DQ31 CB4 CB5 VDD CK0 /CK0 Pin No. 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Pin name DQ53 NC VDD DM6/DQS15 DQ54 DQ55 VDD NC DQ60 DQ61 VSS DM7/DQS16 DQ62 DQ63 VDD SA0 SA1 SA2 VDDSPD
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DQ26 40 41 42 43 44 DQ27 A2 VSS A1 CB0 45 46 CB1 VDD
Preliminary Data Sheet E0376E10 (Ver. 1.0)
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EBD51RD8ABFA
Pin Description
Pin name A0 to A12 BA0, BA1 DQ0 to DQ63 CB0 to CB7 /RAS /CAS /WE /CS0 Function Address input Row address Column address Data input/output Check bit (Data input/output) Row address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input and output data strobe Input mask Clock input for serial PD Data input/output for serial PD Serial address input Power for internal circuit Power for serial EEPROM Input reference voltage Ground A0 to A12 A0 to A9, A11
Bank select address
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CKE0 CK0 /CK0 DQS0 to DQS8 SCL SDA SA0 to SA2 VDD VDDSPD VREF VSS VDDID /RESET NC
DM0 to DM8/DQS9 to DQS17
Preliminary Data Sheet E0376E10 (Ver. 1.0)
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VDD identification flag No connection
Reset pin (forces register inputs low)
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EBD51RD8ABFA
Serial PD Matrix*
Byte No. 0 1 2 3 4 5 6 7 8 9
1
Function described Number of bytes utilized by module manufacturer Total number of bytes in serial PD device Memory type Number of row address Number of column address Number of DIMM ranks Module data width Module data width continuation
Bit7 1 0 0 0 0 0 0 0
Bit6 0 0 0 0 0 0 1 0 0 1 1 1 1 0 0 0 0 0 0
Bit5 Bit4 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0
Bit3 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 1 1 0 1
Bit2 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 1 1 1 0 0
Bit1 Bit0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 0 0 1 1 1 1 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 1 0
Hex value 80H 08H 07H 0DH 0BH 01H 48H 00H 04H 60H 75H 70H 75H 02H 82H 08H 08H 01H 0EH 04H 0CH 01H 02H 26H
Comments 128 256 byte SDRAM DDR 13 11 1 72 bits 0 (+) SSTL 2.5V CL = 2.5*3
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-7A, -7B 10 -7A, -7B 11 12 13 14 15 16 17 18 19 20 21 22 23 -7B 24 -7A, -7B 25 26 27 -7A, -7B
Voltage interface level of this assembly 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1
DDR SDRAM cycle time, CL = X -6B SDRAM access from clock (tAC) -6B
0.70ns*3 0.75ns*3 ECC 7.8 s Self refresh x8 x8 1 CLK 2, 4, 8 4 2, 2.5 0 1 Registered 0.2V CL = 2*3
DIMM configuration type
Refresh rate/type
Primary SDRAM width
Error checking SDRAM width
SDRAM device attributes: Minimum clock delay back-to-back column access SDRAM device attributes: Burst length supported SDRAM device attributes: Number of banks on SDRAM device SDRAM device attributes: /CAS latency SDRAM device attributes: /CS latency SDRAM device attributes: /WE latency SDRAM module attributes SDRAM device attributes: General
Minimum clock cycle time at CLX - 0.5 0 -6B, -7A 1 Maximum data access time (tAC) from 0 clock at CLX - 0.5 -6B 0 0 Minimum clock cycle time at CLX - 1
Maximum data access time (tAC) from 0 clock at CLX - 1 Minimum row precharge time (tRP) 0 -6B 0
Preliminary Data Sheet E0376E10 (Ver. 1.0)
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0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 1 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0
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1 1 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
C0H 75H
A0H 70H 0.70ns*3 0.75ns*3
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75H 00H 00H 48H 18ns 50H 20ns
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EBD51RD8ABFA
Byte No. 28
Function described Minimum row active to row active delay (tRRD) -6B -7A, -7B Minimum /RAS to /CAS delay (tRCD) -6B -7A, -7B Minimum active to precharge time (tRAS) -6B -7A, -7B
Bit7 0 0 0 0 0 0 1 0 1
Bit6 0 0 1 1 0 0 0 1 0 1 0 1 1 1 1
Bit5 Bit4 1 1 0 0 1 1 0 1 0 1 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 1 0 1
Bit3 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0
Bit2 0 1 0 0 0 1 0 1 0 1 0 1 0 1 0 0 1 0 0 0
Bit1 Bit0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1
Hex value 30H 3CH 48H 50H 2AH 2DH 80H 75H 90H 75H 90H 45H 50H 45H 50H 00H 3CH 41H 48H 4BH
Comments 12ns 15ns 18ns 20ns 42ns 45ns 1 rank 512MB 0.75ns*3 0.9ns*3 0.75ns*3 0.9ns*3 0.45ns*3 0.5ns*3 0.45ns*3 0.5ns*3 Future use 60ns*3 65ns*3 72ns*3 75ns*3 12ns*3 0.45ns*3 0.5ns*3 0.55ns*3 0.75ns*3
29
30
31
Module rank density Address and command setup time before clock (tIS) -6B -7A, -7B
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32 33 -7A, -7B 34 -7A, -7B 35 -7A, -7B 36 to 40 41 -7A, -7B 42 -7A, -7B 43 44 -7A, -7B 45 -7A, -7B 46 to 61 62 63 SPD revision -7A -7B 64 to 65 66 67 to 71
Address and command hold time after 0 clock (tIH) -6B 1 0 0 0 0 Data input setup time before clock (tDS) -6B
Data input hold time after clock (tDH) -6B Superset information
Active command period (tRC) -6B
Auto refresh to active/ Auto refresh command cycle (tRFC) -6B SDRAM tCK cycle max. (tCK max.) Dout to DQS skew -6B Data hold skew (tQHS) -6B Superset information Checksum for bytes 0 to 62 -6B
Manufacturer's JEDEC ID code Manufacturer's JEDEC ID code Manufacturer's JEDEC ID code
Preliminary Data Sheet E0376E10 (Ver. 1.0)
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0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 1 0 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 1 1 1 0 0 1 0 1 0 0 0 0 1 1 1 0 1 0 0 1 1 1 1 1 0 0 0 0 1 0 1 1 1 0
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0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 1 0 0 1 1 1 1 1 0 0 0
30H
2DH 32H
55H 75H
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00H Future use 00H Initial 89 59H 10H 16 3BH 59 7FH FEH 00H Elpida Memory
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EBD51RD8ABFA
Byte No. 72 73 74 75 76 77 78 79 80 81 82 Function described Manufacturing location Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Bit7 x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x Bit6 x 1 1 1 0 0 1 1 0 1 1 1 1 0 0 0 1 1 0 0 0 x x Bit5 Bit4 x 0 0 0 1 1 0 0 1 0 0 0 0 1 1 1 0 0 1 1 1 x x x 0 0 0 1 1 1 0 1 0 0 0 0 0 1 1 0 0 0 1 0 x x Bit3 x 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 x x Bit2 x 1 0 1 1 0 0 1 0 0 0 1 0 1 1 1 0 0 0 0 0 x x Bit1 Bit0 x 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 1 0 0 0 x x x 1 0 0 1 1 0 0 0 1 0 0 1 1 0 1 1 0 0 0 0 x x Hex value xx 45H 42H 44H 35H 31H 52H 44H 38H 41H 42H 46H 41H 2DH 36H 37H 41H 42H 20H 30H 20H xx xx Comments *2 (ASCII-8bit code) E B D 5 1 R D 8 A B F A -- 6 7 A B (Space) Initial (Space) Year code (HEX) Week code (HEX)
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83 84 85 86 -7A, -7B 87 -6B, -7B 88 to 90 91 92 93 94 95 to 98 99 to 127 Revision code Revision code
Module part number Module part number Module part number -6B Module part number -7A
Module part number
Manufacturing date Manufacturing date Module serial number
Manufacturer specific data
Notes: 1. All serial PD data are not protected. 0: Serial data, "driven Low", 1: Serial data, "driven High" 2. Bytes 95 through 98 are assembly serial number. 3. These specifications are defined based on component specification, not module.
Preliminary Data Sheet E0376E10 (Ver. 1.0)
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EBD51RD8ABFA
Block Diagram
/RCS0 RS DM0/DQS9 RS DQS0 8 DQ0 to DQ7 RS DQS I/O0 to I/O7 DM /CS DM4/DQS13 RS RS DM DQS 8 DQ32 to DQ39 RS I/O0 to I/O7 /CS
D0
DQS4
D4
RS DM1/DQS10 RS DQS1 8 DQ8 to DQ15 RS DQS I/O0 to I/O7 DM
/CS DM5/DQS14
RS DM RS DQS 8 DQ40 to DQ47 RS I/O0 to I/O7
/CS
D1
DQS5
D5
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VDD VREF VSS
RS DM2/DQS11 RS DQS2 8 DQ16 to DQ23 RS DQS I/O0 to I/O7 DM
/CS DM6/DQS15
RS DM RS DQS 8 DQ48 to DQ55 RS I/O0 to I/O7
/CS
D2
DQS6
D6
RS DM3/DQS12 DQS3 DM DQS I/O0 to I/O7 RS
/CS DM7/DQS16
RS DM RS DQS 8 DQ56 to DQ63 RS I/O0 to I/O7
/CS
Preliminary Data Sheet E0376E10 (Ver. 1.0)
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8 DQ24 to DQ31 DM8/DQS17 DQS8 8 CB0 to CB7
/CS0 BA0 to BA1 A0 to A12 /RAS /CAS CKE0 /WE
RS RS RS RS RS RS RS
D3
DQS7
D7
RS
RS RS RS
/CS DM
Pr
DQS
D8
I/O0 to I/O7
/RCS0 -> /CS: SDRAMs D0 to D8
R E G I S T E R
RBA0 to RBA1 -> BA0 to BA1: SDRAMs D0 to D8 RA0 to RA12 -> A0 to A12: SDRAMs D0 to D8 /RRAS -> /RAS: SDRAMs D0 to D8 /RCAS -> /CAS: SDRAMs D0 to D8
* D0 to D8: 512M bits DDR SDRAM U0: 2k bits EEPROM RS: 22 PLL: CDCV857 Register: SSTV16857 Serial PD
RCKE0 -> CKE: SDRAMs D0 to D8 /RWE -> /WE: SDRAMs D0 to D8 /RESET D0 to D8 D0 to D8 D0 to D8
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SCL SCL SDA
SDA
U0
A1
PCK /PCK
A0
A2
VDDID open CK0, /CK0 PLL* Note: Wire per Clock loading table/Wiring diagrams.
SA0 SA1 SA2 Notes: 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state.
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EBD51RD8ABFA
Differential Clock Net Wiring (CK0, /CK0)
0ns (nominal)
PLL OUT1
SDRAM
120
CK0
120 IN 240
Capacitance
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/CK0
Register1
120
OUT'N'
(Typically two registers per DIMM)
C Feedback 240 Register2
Notes: 1. The clock delay from the input of the PLL clock to the input of any SDRAM or register will be set to 0 ns (nominal). 2. Input, output and feedback clock lines are terminated from line to line as shown, and not from line to ground. 3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired in a similar manner. 4. Termination resistors for feedback path clocks are located after the pins of the PLL. 5. SDRAM clock pair inputs have a parallel capacitor equal to one-half nominal SDRAM input clock load.
Preliminary Data Sheet E0376E10 (Ver. 1.0)
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Electrical Specifications
* All voltages are referenced to VSS (GND). Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating ambient temperature Storage temperature Symbol VT VDD IOS PD TA Tstg Value -1.0 to +3.6 -1.0 to +3.6 50 9 0 to +70 -55 to +125 Unit V V mA W C C 1 Note
Note: 1. DDR SDRAM component specification Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
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Parameter Supply voltage Input reference voltage Termination voltage Input high voltage Input low voltage Input voltage level, CK and /CK inputs Input differential cross point voltage, CK and /CK inputs Input differential voltage, CK and /CK inputs
DC Operating Conditions (TA = 0 to +70C) (DDR SDRAM component Specification)
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Symbol VSS VREF VTT VIH (DC) VIL (DC) VIN (DC) VIX (DC) VID (DC)
Min 2.3 0 0.49 x VDDQ VREF - 0.04 VREF + 0.15
Typ 2.5 0 0.50 x VDDQ VREF --
Max 2.7 0 0.51 x VDDQ VREF + 0.04 VDDQ + 0.3 VREF - 0.15 VDDQ + 0.3
Unit V V V V V V V
Notes 1
VDD,VDDQ
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-0.3 -- -0.3 -- 0.5 x VDDQ - 0.2V 0.36 --
2 3 4
0.5 x VDDQ
0.5 x VDDQ + 0.2V V VDDQ + 0.6 V 5, 6
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Notes: 1. 2. 3. 4. 5. 6.
VDDQ must be lower than or equal to VDD. VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns. VIL is allowed to outreach below VSS down to -1.0V for the period shorter than or equal to 5ns. VIN (DC) specifies the allowable DC execution of each differential input. VID (DC) specifies the input differential voltage required for switching. VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF - 0.18V if measurement.
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Preliminary Data Sheet E0376E10 (Ver. 1.0)
EBD51RD8ABFA
DC Characteristics 1 (TA = 0 to +70C, VDD = 2.5V 0.2V, VSS = 0V)
Parameter Operating current (ACTV-PRE) Operating current (ACTV-READ-PRE) Symbol IDD0 IDD1 Grade -6B -7A, -7B -6B -7A, -7B -6B -7A, -7B max. 1740 1605 2010 1830 417 750 705 615 570 -6B -7A, -7B -6B -7A, -7B -6B -7A, -7B -6B -7A, -7B 1020 930 2280 2010 2280 2010 3000 2820 426 -6B -7A, -7B 4260 3720 Unit mA mA mA mA mA mA mA mA mA mA mA mA Test condition CKE VIH, tRC = tRC (min.) CKE VIH, BL = 4, CL = 3.5, tRC = tRC (min.) CKE VIL CKE VIH, /CS VIH, DQ, DQS, DM = VREF CKE VIH, /CS VIH, DQ, DQS, DM = VREF CKE VIL CKE VIH, /CS VIH tRAS = tRAS (max.) CKE VIH, BL = 2, CL = 3.5 CKE VIH, BL = 2, CL = 3.5 tRFC = tRFC (min.), Input VIL or VIH Input VDD - 0.2 V Input 0.2 V BL = 4 Notes 1, 2, 9 1, 2, 5 4 4, 5 4, 10 3 3, 5, 6 1, 2, 5, 6 1, 2, 5, 6
Idle power down standby current IDD2P Floating idle standby current Quiet idle standby current Active power down standby current IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7A
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Active standby current Operating current (Burst read operation) Operating current (Burst write operation) Auto refresh current Self refresh current Operating current (4 banks interleaving) Parameter Input leakage current Output leakage current Output high current Output low current ILI
5, 6, 7
Notes. 1. These IDD data are measured under condition that DQ pins are not connected. 2. One bank operation. 3. One bank active. 4. All banks idle. 5. Command/Address transition once per one cycle. 6. DQ, DM and DQS transition twice per one cycle. 7. 4 banks active. Only one bank is running at tRC = tRC (min.) 8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general. 9. Command/Address transition once every two clock cycles. 10. Command/Address stable at VIH or VIL.
DC Characteristics 2 (TA = 0 to +70C, VDD, VDDQ = 2.5V 0.2V, VSS = 0V) (DDR SDRAM component Specification)
Symbol min. -2 -5 -15.2 15.2
Preliminary Data Sheet E0376E10 (Ver. 1.0)
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max. 2 A 5 A -- -- mA mA
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Unit
Test condition
Notes
VDD VIN VSS VDDQ VOUT VSS VOUT = 1.95V
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VOUT = 0.35V
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EBD51RD8ABFA
Pin Capacitance (TA = 25C, VDD = 2.5V 0.2V)
Parameter Input capacitance Input capacitance Data and DQS input/output capacitance Symbol CI1 CI2 CO Pins Address, /RAS, /CAS, /WE, /CS, CKE CK, /CK DQ, DQS, CB, DM max. 10 20 15 Unit pF pF pF Notes 1, 3 1, 3 1, 2, 3
Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VDDQ/2, VOUT = 0.2V. 2. Dout circuits are disabled. 3. This parameter is sampled and not 100% tested. AC Characteristics (TA = 0 to +70C, VDD, VDDQ = 2.5V 0.2V, VSS = 0V)
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Parameter Clock cycle time (CL = 2) (CL = 2.5) CK high-level width CK low-level width CK half period DQ output access time from CK, /CK DQS to DQ skew Data hold skew factor Read preamble Read postamble DQ and DM input setup time DQ and DM input hold time Write preamble setup time Write preamble Write postamble DQS input high pulse width DQS input low pulse width
(DDR SDRAM component Specification)
-6B Symbol tCK tCK tCH tCL min. 7.5 6 0.45 0.45 min (tCH, tCL) -0.7 max 12 12 0.55 0.55 -- 0.7 0.6 0.45 -7A min. 7.5 7.5 0.45 0.45 min (tCH, tCL) -0.75 -0.75 -- max 12 12 0.55 0.55 -- 0.75 0.75 0.5 -7B min. 10 7.5 0.45 0.45 min (tCH, tCL) -0.75 -0.75 -- max 12 12 0.55 0.55 -- 0.75 0.75 0.5 Unit Notes ns ns tCK tCK tCK ns ns ns ns ns ns ns tCK tCK ns ns ns ns tCK 8 8 7 5, 11 6, 11 2, 11 2, 11 3 10
DQS output access time from CK, /CK tDQSCK -0.6 tDQSQ --
DQ/DQS output hold time from DQS
Data-out high-impedance time from tHZ CK, /CK Data-out low-impedance time from CK, tLZ /CK
DQ and DM input pulse width
Write command to first DQS latching transition DQS falling edge to CK setup time DQS falling edge hold time from CK
Address and control input setup time Address and control input hold time
Preliminary Data Sheet E0376E10 (Ver. 1.0)
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tHP tAC tQH tQHS tRPRE tRPST tDS tDH tDIPW tWPRE tWPST tDQSS tDSS tDSH tDQSH tDQSL tIS tIH
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tHP - tQHS -- -- 0.55 -- -0.7 0.7 -0.75 -0.7 0.9 0.4 0.45 0.45 1.75 0.7 -0.75 0.9 1.1 0.6 -- 0.4 0.5 -- 0.5 -- 1.75 tWPRES 0 0.25 0.4 0.75 0.2 0.2 0.35 0.35 0.75 0.75 -- 0 -- 0.25 0.6 1.25 -- -- -- -- -- -- 0.4 0.75 0.2 0.2 0.35 0.35 0.9 0.9
tHP - tQHS -- 0.75 0.75 0.75 1.1
tHP - tQHS -- -- -0.75 -0.75 0.9 0.75 0.75 0.75 1.1 0.6 -- -- -- -- --
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0.6 -- 0.4 0.5 -- 0.5 -- 1.75 -- -- 0 0.25 0.6 0.4 1.25 -- -- 0.75 0.2 0.2 -- -- 0.35 0.35 0.9 -- -- 0.9
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0.6 tCK 9 1.25 -- tCK tCK -- tCK -- tCK -- tCK -- ns 8 -- ns 8
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EBD51RD8ABFA
-6B Parameter Address and control input pulse width Symbol tIPW min. 2.2 2 42 60 72 18 18 tRCD min. 12 15 max -- -- 120000 -- -- -- -- -- -- -- -7A min. 2.2 2 45 65 75 20 20 tRCD min. 15 15 max -- -- 120000 -- -- -- -- -- -- -- -7B min. 2.2 2 45 65 75 20 20 tRCD min. 15 15 max -- -- 120000 -- -- -- -- -- -- -- Unit Notes ns tCK ns ns ns ns ns ns ns ns tCK tCK s 13 7
Mode register set command cycle time tMRD Active to Precharge command period tRAS Active to Active/Auto refresh command tRC period Auto refresh to Active/Auto refresh tRFC command period Active to Read/Write delay Precharge to active command period Active to auto precharge delay Active to active command period Write recovery time Auto precharge write recovery and precharge time Average periodic refresh interval tRCD tRP tRAP tRRD tWR tDAL
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(tWR/tCK)+ -- (tRP/tCK) 1 -- -- 7.8
(tWR/tCK)+ -- (tRP/tCK) 1 -- -- 7.8
(tWR/tCK)+ -- (tRP/tCK) 1 -- -- 7.8
Internal write to Read command delay tWTR tREF
Notes: 1. All the AC parameters listed in this data sheet is component specifications. For AC testing conditions, refer to the corresponding component data sheet. 2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal transition is defined to occur when the signal level crossing VTT. 3. The timing reference level is VTT. 4. Output valid window is defined to be the period between two successive transition of data out or DQS (read) signals. The signal transition is defined to occur when the signal level crossing VTT. 5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage level, but specify when the device output stops driving. 6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This parameter is not referred to a specific DOUT voltage level, but specify when the device output begins driving. 7. Input valid windows is defined to be the period between two successive transition of data input or DQS (write) signals. The signal transition is defined to occur when the signal level crossing VREF. 8. The timing reference level is VREF. 9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific reference voltage to judge this transition is not given. 10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not assured. 11. tCK = tCK (min.) when these parameters are measured. Otherwise, absolute minimum values of these values are 10% of tCK. 12. VDD is assumed to be 2.5V 0.2V. VDD power supply variation per cycle expected to be less than 0.4V/400 cycle. 13. tDAL = (tWR/tCK)+(tRP/tCK) For each of the terms above, if not already an integer, round to the next highest integer. Example: For -7A Speed at CL = 2.5, tCK = 7.5ns, tWR = 15ns and tRP= 20ns, tDAL = (15ns/7.5ns) + (20ns/7.5ns) = (2) + (3) tDAL = 5 clocks
Preliminary Data Sheet E0376E10 (Ver. 1.0)
L
Pr
13
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EBD51RD8ABFA
Timing Parameter Measured in Clock Cycle for Registered DIMM
Number of clock cycle tCK Parameter Write to pre-charge command delay (same bank) Read to pre-charge command delay (same bank) Write to read command delay (to input all data) Burst stop command to write command delay (CL = 3) Symbol tWPD tRPD tWRD tBSTW tBSTW tBSTZ tBSTZ tRWD tRWD tHZP tHZP 6ns min. 4 + BL/2 BL/2 2 + BL/2 -- 3 -- 3.5 -- 3 + BL/2 -- 3.5 2 2 2 12 -- 3.5 2 -- 3.5 -- -- max. 7.5ns min. 3 + BL/2 BL/2 2 + BL/2 2 3 3 3.5 2 + BL/2 3 + BL/2 3 3.5 2 1 2 10 200 1 1 1 3 3.5 2 3 3.5 max. Unit tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK
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(CL = 3.5) (CL = 3.5) (CL = 3.5) (CL = 3.5) Write recovery Power down entry
Burst stop command to DQ High-Z (CL = 3) Read command to write command delay (to output all data) (CL = 3) Pre-charge command to High-Z (CL = 3)
Write command to data in latency
Register set command to active or register set command Self refresh exit to read command
Self refresh exit to non-read command tSNR
Power down exit to command input
Preliminary Data Sheet E0376E10 (Ver. 1.0)
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tWR tSRD
tWCD
tMRD
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200 1 tPDEN 1 tPDEX 1
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14
EBD51RD8ABFA
Pin Functions
CK, /CK (input pin) The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross point of the CK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross point of the CK and the /CK. When a write operation, DMs and DQs are referred to the cross point of the DQS and the VREF level. DQSs for write operation are referred to the cross point of the CK and the /CK. /CS (input pin) When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. /RAS, /CAS, and /WE (input pins) These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. See "Command operation". A0 to A12 (input pins) Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the VREF level in a bank active command cycle. Column address (AY0 to AY9, AY11) is loaded via the A0 to the A9 and the A11 at the cross point of the CK rising edge and the VREF level in a read or a write command cycle. This column address becomes the starting address of a burst operation. A10 (AP) (input pin) A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = high when read or write command, auto-precharge function is enabled. While A10 = low, auto-precharge function is disabled. BA0, BA1 (input pin) BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See Bank Select Signal Table)
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Bank 0 Bank 1 Bank 2 Bank 3
[Bank Select Signal Table]
Remark: H: VIH. L: VIL.
CKE (input pin) CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the CKE is driven low and exited when it resumes to high. The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge and the VREF level with proper setup time tIS, at the next CK rising edge CKE level must be kept with proper hold time tIH. DQ, CB (input and output pins) Data are input to and output from these pins.
DQS (input and output pin) DQS provide the read data strobes (as output) and the write data strobes (as input).
Preliminary Data Sheet E0376E10 (Ver. 1.0)
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L H L H
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BA0
BA1 L L
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H H
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15
EBD51RD8ABFA
DM (input pins): DM is the reference signal of the data input mask function. DMs are sampled at the cross point of DQS and VREF VDD (power supply pins) 2.5V is applied. (VDD is for the internal circuit.) VDDSPD (power supply pin) 2.5V is applied (For serial EEPROM). VSS (power supply pin) Ground is connected. /RESET (input pin) LVCMOS reset input. When /RESET is low, all registers are reset and all outputs are low.
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Detailed Operation Part and Timing Waveforms
Refer to the EDD5104AB, EDD5108AB datasheet (E0237E). DIMM /CAS latency = component CL + 1 for registered type.
Preliminary Data Sheet E0376E10 (Ver. 1.0)
L Pr od t uc
16
EBD51RD8ABFA
Physical Outline
Unit: mm 133.35 0.15 128.95 4.80 (64.48) (DATUM -A-)
2.30
Component area (Front)
1 B A 49.53 92
64.77
1.27 0.10
2 - 2.50 0.10
93
10.00
184
4.00 min
4.00 0.10
2.50 0.20
0.20 0.15
3.80
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R 2.00
Component area (Back)
3.00 min
Detail A
Detail B 1.27 typ 6.62 2.175 R 0.90 (DATUM -A-)
6.35
1.00 0.05
1.80 0.10
Note: Tolerance on all dimensions 0.13 unless otherwise specified.
ECA-TS2-0058-01
Preliminary Data Sheet E0376E10 (Ver. 1.0)
17
30.48 0.15
17.80
L
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EBD51RD8ABFA
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. In particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. When re-packing memory modules, be sure the modules are not touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
MDE0202
NOTES FOR CMOS DEVICES
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1 2 3
PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
Preliminary Data Sheet E0376E10 (Ver. 1.0)
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Pr
18
od
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CME0107
EBD51RD8ABFA
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
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Preliminary Data Sheet E0376E10 (Ver. 1.0)
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19
M01E0107
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t uc

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